HP (NYSE: HWP) announced its BL495C, claiming the first blade designed for virtualization.

Overview The HP ProLiant BL495c virtualization blade is the world’s first server blade designed specifically to host virtual machines. The BL495c is the ideal platform for virtualized environments that require significant memory, data storage and network connections to optimize server performance.

The BL495c eliminates performance bottlenecks by accelerating virtual server speed with twice the memory capacity, solid state drives that use significantly less power, and up to two more Ethernet network connections than competitive offerings.(1) Based on the typical configuration of 4 gigabytes (GB) per virtual machine (VM), the BL495c can support a minimum of 32 VMs. Customers filling an HP BladeSystem c7000 enclosure with 16 BL495c server blades can utilize up to 512 VMs versus 256 and 112 from the closest competitors.(2)

“Customers looking to maximize the performance of their virtualized infrastructure have the answer with the BL495c. It was architected and optimized specifically for virtual machines,” said Mark Potter, vice president, HP BladeSystem. “With its memory, storage and I/O capabilities, the BL495c is unmatched in the industry and redefines server blades for virtualization.”

The BL495C ships with 10GB NICs.  In a video on this page, HP specifically points out comparisons vs. IBM and Dells used of 1GB NIC and half the DIMM slots.  HP’s support for SSD also is another point. 

10GB vs 1 GB. 2 times the DIMMs. Support for SSD.

It is interesting that HP has added all this IO capability to dual proc, quadcore AMD blade. This supports the idea that IO is the big issue in virtualization hardware.

This announcement was part of a bigger HP Virtualization initiative.

HP Encourages CIOs to Rethink Virtualization in Business Terms

HP has expanded its industry-leading virtualization portfolio to maximize better business outcomes for customers. To meet the growing demands of technology environments, HP is providing businesses with the virtualization tools and strategies needed to rethink infrastructure management, client architectures and barriers to building and organizing infrastructures.

HP's latest hardware, software and services offerings enable enterprises to blend physical and virtual assets to expand virtualization beyond the data center, providing new ways for customers to accelerate growth, lower cost and mitigate risk.

Ars Technica has technical details on Intel’s power gating and turbo mode.

First an overview

Power gating, turbo mode, and the PCU

Most of the Nehalem disclosures in Gelsinger's keynote, and in the subsequent technical session on Nehalem, had to do with the new microarchitecture's power management capabilities. With Nehalem, Intel is introducing a technology that it calls "power gating." Traditionally, Intel has been able shut down an unused core by cutting its active power, but even though it's in a sleep state, that core is still dissipating plenty of power because of leakage current. Intel's power gating technique involves a new transistor design, and it lets Intel cut the leakage current, as well, so that the sleeping core's power dissipation drops to near zero.

When one or more of the cores on a Nehalem chip are powered down, the processor can divert extra power to the cores that are in use by increasing their clockspeed and voltage. (This is kind of like the "divert power to the main thrusters," thing that Scottie would always do in Star Trek.) This gives the active cores extra performance headroom while permitting the overall processor to remain in the same power envelope, and Gelsinger noted that it effectively gives each core two extra speed bins worth of performance.

Here are technical details on what is on the chip.

Nehalem's power gating, turbo mode, and other dynamic power saving features involve a complex coordination of a huge array of on-die sensors and circuit blocks on different parts of the chip, a feat that would have been impossible to pull off on a four- or eight-core processor without some centralized means of processing sensor data and orchestrating the power changes. So for Nehalem, Intel's designers have introduced a brand new major functional block, the power control unit (PCU).

Nehalem's PCU is a relatively large programmable microcontroller that uses firmware to implement various sophisticated power optimization algorithms, and committing such large amount of die space to such a complex block is a fairly dramatic move, especially in the name of power savings. I don't remember the exact transistor count (it's in the millions, and Gelsinger remarked that it was the size of a 486), but Intel is paying a hefty price in transistors and power for this unit. This being the case, it must have a dramatic impact on Nehalem's overall power consumption under load if it's able to more than pay for itself in net power savings.

It will be interesting what the real world performance tests show.