Technical Details Behind Intel’s Power Gating & Turbo Mode

Ars Technica has technical details on Intel’s power gating and turbo mode.

First an overview

Power gating, turbo mode, and the PCU

Most of the Nehalem disclosures in Gelsinger's keynote, and in the subsequent technical session on Nehalem, had to do with the new microarchitecture's power management capabilities. With Nehalem, Intel is introducing a technology that it calls "power gating." Traditionally, Intel has been able shut down an unused core by cutting its active power, but even though it's in a sleep state, that core is still dissipating plenty of power because of leakage current. Intel's power gating technique involves a new transistor design, and it lets Intel cut the leakage current, as well, so that the sleeping core's power dissipation drops to near zero.

When one or more of the cores on a Nehalem chip are powered down, the processor can divert extra power to the cores that are in use by increasing their clockspeed and voltage. (This is kind of like the "divert power to the main thrusters," thing that Scottie would always do in Star Trek.) This gives the active cores extra performance headroom while permitting the overall processor to remain in the same power envelope, and Gelsinger noted that it effectively gives each core two extra speed bins worth of performance.

Here are technical details on what is on the chip.

Nehalem's power gating, turbo mode, and other dynamic power saving features involve a complex coordination of a huge array of on-die sensors and circuit blocks on different parts of the chip, a feat that would have been impossible to pull off on a four- or eight-core processor without some centralized means of processing sensor data and orchestrating the power changes. So for Nehalem, Intel's designers have introduced a brand new major functional block, the power control unit (PCU).

Nehalem's PCU is a relatively large programmable microcontroller that uses firmware to implement various sophisticated power optimization algorithms, and committing such large amount of die space to such a complex block is a fairly dramatic move, especially in the name of power savings. I don't remember the exact transistor count (it's in the millions, and Gelsinger remarked that it was the size of a 486), but Intel is paying a hefty price in transistors and power for this unit. This being the case, it must have a dramatic impact on Nehalem's overall power consumption under load if it's able to more than pay for itself in net power savings.

It will be interesting what the real world performance tests show.