Computer Architecture developed for Speed and Power

Micorsoft Research has another project which can change the data center, and make in Greener.  The following are excerpts from their postChuck Thacker is the architect behind the project and as an experienced computer architect who gets how power is an issue in computer architectures and data centers. Chuck is one of the Microsoft Research people who has an interest in what is going on in Microsoft data centers.

Indeed, speed and power are the two attributes Thacker hopes the BEE3 system can help address.

“One of the big problems that we face as a company is that it’s become increasingly clear that processors aren’t going to get faster,” he says. “They dissipate too much power now, and it’s a real challenge to get rid of it. We want to look at some of these new architectures as possibilities for solving those two problems, the speed problem and the power problem.”

And, his colleague John Davis is working on the instrumentation for the system. 

“One of the nice things about these systems is that they can be very intricately instrumented, so we can get a lot of data.”

“They designed the case of the system,” Thacker says. “They designed the heat sinks for the FPGAs and did all the computational fluid-dynamic modeling to make sure that it would all work. That is one of the largest mistakes you can make in designing a computer system, to get the thermal properties wrong, because then it overheats and doesn’t work. Function was enormously helpful in this area.”

A dream scenario is these guys leave the option to have instrumentation embedded in the design if they go to production.

Another way to solve the power utilization issue is to build custom computers.

The viability of the FPGA approach was demonstrated last summer, when Zhangxi Tan, then an intern at Microsoft Research Silicon Valley, built a system for solving the problem of binary satisfiability, commonly used in design automation.

“He got speed of about 40 times what a computer could do,” Thacker reports, “because the algorithm is exactly suited for what can be done in FPGAs.”