news.com has a post on ARM’s new processor announcement.
ARM eyes Intel turf with 2GHz multicore designs
by Rupert Goodwins
Cambridge, England-based chip company ARM on Wednesday announced the development of dual-core, quad-core, and eight-core Cortex A9 processor designs, explicitly aimed at markets currently served by Intel's x86 chips and IBM's PowerPC.
"This is a huge departure from what we've done in the past", Eric Schorn, vice president of marketing for ARM's processor division, told ZDNet UK. "We really wanted to take off the handcuffs and see what could be done with performance, performance, performance."
The new designs, available in two variants optimized for low power consumption or high performance, are intended for use by companies building their own chips. ARM claims that the new processors, which can run at up to 2GHz, are up to eight times more efficient than Intel's low-power chips in terms of performance per watt, with the high-performance part running at five times the throughput of Intel's Atom chip for similar power levels.
The low-power part delivers twice the performance at a quarter the power, according to the company's published benchmarks.
A technical demonstration of an ARM server is running here.
This website runs on experimental ARM based servers based around the Marvell MV78100 SoC.
Each server blade has:
7 of the these server blades are mounted into a custom built single rack with one 240VAC to 12VDC PSU to power all seven blades.
- a single MV78100
- 1 x 2.5inch 7400rpm SATA HDD
- 1.5GBytes of DDR 2 RAM
There is no forced cooling in the system.
The OS is the ARM port of Debian Lenny.
The board is monitored by an ARM mbed prototype energy monitoring and control board. The counter in the footer of the site makes a crude estimate of the energy consumed while rendering each page.
If you wonder if any of the data center folks are paying attention, here is Amazon’s James Hamilton post.
The ARM is a clear win on work done per dollar and work done per joule for some workloads. If a 4-core, cache coherent version was available with a reasonable memory controller, we would have a very nice server processor with record breaking power consumption numbers.
I got a call from ARM soon after posting saying that I may get my wish sooner than I was guessing. Very cool. The Design that was announced earlier today includes a 2-core, performance optimized design that could form the building block of a very nice server. In the following block diagram, ARM shows a pair of 2-core macros implementing a 4-way SMP:
The ARM reported performance results: